1. Field of the Invention
The present invention relates to a ferroelectric memory, and more particularly, to a reference voltage supply apparatus for use in a ferroelectric memory device and a driving method thereof.
2. Description of the Related Art
Consumer and industrial demand for non-volatile memory devices is increasing. A ferroelectric random access memory (FRAM) using a ferroelectric thin film for a dielectric material, as in a DRAM (Dynamic Random Access Memory) memory cell's capacitor, is a non-volatile memory device, and has the merits of storing information in an unpowered state and of high-speed access, low power consumption and endurance against impact. A ferroelectric memory cell consists of a ferroelectric capacitor and an access switch (e.g., a field effect, FET or MOS transistor.). Its structure is similar to the storage cell of a DRAM. The difference is in the dielectric properties of the material between the capacitor's electrodes. This ferroelectric material has a high dielectric constant and can be polarized by an applied electric field. A residual polarization remains until it is coercively reversed by an opposite applied electric field. This makes the FRAM memory non-volatile. Note that “ferroelectric” material, despite its name, does not necessarily contain iron. The most well-known ferroelectric substance is BaTiO3, which does not contain iron.
Data is “read” out of a FRAM by applying an electric field to the capacitor. If this “switches” the cell into the opposite state (flipping over the electrical dipoles in the ferroelectric material) then more charge is moved during the read than if the cell was not flipped. This can be detected and amplified by sense amplifiers (S/A). Reading destroys the contents of a cell which must therefore be written back after a read. This is operation is similar to the precharge operation in DRAM, but it only needs to be done after a read rather than periodically as with DRAM refresh. Thus, FRAM devices are capable of overcoming the limitations of other memory devices, including the periodic refresh necessary for a DRAM (Dynamic Random Access Memory) device, by using a ferroelectric thin film for a dielectric film of a capacitor.
The use of FRAM memory devices is expected to increase, as a main memory (e.g., RAM, random access memory) in various kinds of electronic equipment having file storage and search functions such as portable computers, cellular phones and gaming machines etc., and for use as a removable recording medium (e.g., flash memory cards) for recording voice or images or video (e.g., music players, digital cameras, digital video recorders, etc.). Other devices potentially using FRAM memory includes office equipment (such as printers and copier machines), home appliances (microwaves ovens and washing machines, for instance) and industrial equipment (power meters).
When a voltage is applied to both ends of a ferroelectric capacitor, the ferroelectric material is polarized in the direction of the applied electric field. A switching threshold voltage at which a polarization state of the ferroelectric material is changed, is a coercive (forcing) voltage. In a FRAM device, a memory cell constructed of a ferroelectric capacitor and an access switch (transistor) stores data of logic state (e.g., ‘1’ or ‘0’) in the electric polarization state of a ferroelectric capacitor. To read data stored in a memory cell, a voltage is applied to generate a voltage difference between the electrodes of the ferroelectric capacitor, and the data state stored in the memory cell is sensed by the amount of charge excited (passed) to a bit line.
FIG. 1 illustrates a typical hysteresis curve for the ferroelectric material of the ferroelectric capacitor (e.g., see FIG. 2). FIG. 1 shows the changes of the level of polarization of ferroelectric film as the voltage is changed.
Referring to FIG. 1, when no electric field (e.g., a ground voltage Voss or 0V) is applied is applied across the ferroelectric material, polarization is not generated. When the voltage across the ferroelectric capacitor increases to a positive voltage (+If), polarization or a charge amount increases (e.g., from a zero or a negative charge at state point D) to a state point A of a positive polarization region. At the state point A, the polarization is generated in a positive direction, and a polarization level of the state point A has the maximum value represented as +Qs. Then, even though voltage across the capacitor falls to zero (ground voltage Vss), the polarization level does not fall to zero but remains at a state point B. The charge amount that ferroelectric material retains, a residual polarization, is represented as +Qr. Then, when voltage of both ends of the capacitor decreases to a negative voltage (−Vf), the polarization is changed to a state point C of a negative charge polarization region (from the state point B). At the state point C, the ferroelectric material is polarized to a maximum (negative) polarization, represented as −Qs, in a direction opposite to the polarization direction at state point A. Then, even though the voltage across the capacitor rises to zero (e.g., ground voltage Vss), the polarization level does not rise to zero but remains at a state point D. At this time, the residual (negative) polarization is represented as −Qr. When voltage applied across the capacitor increases again to a positive voltage (e.g., +Vf), the polarization of the ferroelectric material is again changed (back) to the state point A (from the state point D).
A ferroelectric capacitor is formed by inserting ferroelectric material as a dielectric the between two electrodes of the ferroelectric capacitor. When an applied voltage generates electric field across ferroelectric capacitor, then afterwards the applied voltage is removed, even though the electrodes are in a floating state a polarization (residual charge across the dielectric) is maintained. The residual charge of ferroelectric material is not lost naturally by leakage etc. If voltage is not applied in an opposite direction (e.g., so that polarization becomes forced to zero), a residual polarization charge and direction is maintained intact.
When a voltage is applied in a plus direction to the ferroelectric capacitor and is then removed, residual polarization of ferroelectric material becomes a state of +Qr. When a voltage is applied in a negative direction to the ferroelectric capacitor and is then removed, residual polarization of the ferroelectric material becomes a state of −Qr.
Herein, a residual polarization state of +Qr (at state point B) represents a binary logic state of data ‘0’; and a residual polarization state of −Qr, (at a state point D), represents a binary logic state of data ‘1’.
The charge amount in changing from the state point A to the state point B, (e.g., corresponding to the amount of non-switching capacitance Qnsw), is distinguishable from the charge amount in changing from the state point D to the state point A, namely, (corresponding to the amount of switching capacitance Qsw), thereby enabling the reading of data (‘0’ or ‘1’) stored in the FRAM memory cell.
FIG. 2 illustrates a typical 1T-1C (one transistor, one capacitor) memory cell of a ferroelectric memory cell array according to the prior art.
With reference to FIG. 2, a ferroelectric memory cell consists of one switch (e.g., field effect access transistor M1) and one ferroelectric capacitor (CFE). The access transistor M1 has two terminals, (a source terminal and a drain terminal), which are connected between one terminal of the ferroelectric capacitor CFE and a bit line BL. A gate (terminal) of the access transistor (switch) M1 is connected to (controlled by) a word line WL. One terminal of the ferroelectric capacitor CFE is thus switchably connected to the bit line through the access transistor M1, and another terminal of the ferroelectric capacitor CFE is conductively connected to a common plate line PL (e.g., together with a plurality of other ferroelectric capacitors of other memory cells).
In a typical read operation for data stored in a ferroelectric memory cell as described above, to sense and amplify a micro change of voltage excited (passed) to a bit line in a sense amplifier, a specific reference voltage generating apparatus is needed to generate a reference voltage having around medium voltage value between a bit line voltage value in reading data ‘1’ and a bit line voltage value in reading data ‘0’.
There are two methods generating the reference voltage: using a paraelectric capacitor; and using a ferroelectric capacitor. In the method using a paraelectric capacitor having a small dielectric property, the on-chip area of the capacitor is relatively large and is thus inappropriate for a high-integration (high density) memory. The method using a ferroelectric capacitor is subdivided into two: that is, a method of limiting the size of the ferroelectric capacitor and using, as a reference voltage, a capacitance of a non-switching region of a hysteresis curve shown in FIG. 1, a Qnsw value; and a method of using both the switching capacitance and the non-switching capacitance and using a average value of the two values. In addition there is a method of using, as a reference value, a capacitance of a switching region of the hysteresis curve shown in FIG. 1, a Qsw value.
It is challenging to provide a stabilized reference voltage on-chip. This becomes a cause of lowering reliability of ferroelectric memory devices.
FIG. 3 illustrates a FRAM memory device (i.e., a ferroelectric memory device) that includes a reference voltage generating apparatus using a non-switching region capacitance of a conventional ferroelectric capacitor.
As shown in FIG. 3, a FRAM having a conventional reference voltage generating apparatus includes a main memory cell array having a plurality of ferroelectric memory cells MC, word line decoder and driver circuits 22a, 22b, 22c and 22d, a plate line driver circuit 24, a reference voltage supply apparatus 10 that has a reference cell array having a plurality of reference cells RC, and a sense amplifier S/A.
The main memory cell array is constructed of memory cells MC having the structure of the ferroelectric memory cell of FIG. 2. Thus, respective memory cells MC are constructed of one ferroelectric capacitor CFE and one access transistor M1. The memory cells MC are arrayed on intersections of word lines and bit lines. The access transistor (switch) in each memory cell MC is connected to one word line (e.g., SWL0, SWL1, SWL2, of SWL3). One terminal of the ferroelectric capacitor in each memory cell MC is connected to the plate line (e.g., PL0), and the other terminal thereof is connected to a bit line (e.g., BL0, BL1, BL2, BL3) through its respective access transistor (M1).
The word lines SWL0, SWL1, SWL2, SWL3 are respectively connected with word line decoder and driver circuits 22a, 22b, 22c and 22d. The plate line PL0 is connected to a plate line driver circuit 24 for providing a plate line enable signal to the plate line PL0 in response to a plate driver enable signal.
The reference voltage supply apparatus 10 includes a reference cell array (comprised of a plurality of reference cells RC, 10a), reference word line decoder and driver circuits 12a and 12b for providing a reference word line enable signal to respective reference word lines RSWL0 and RSWL1, and a reference plate line driver 14 for providing a reference plate line enable signal to a reference plate line RPL.
A reference cell RC of the reference cell array is constructed of one ferroelectric capacitor and one access transistor, and has the same as or similar structure as the structure of ferroelectric main memory cell MC.
A ferroelectric capacitor of a reference cell RC has a capacitance (e.g., area) larger than a ferroelectric capacitor of the memory cell MC. Reference cells RC having the same as or similar structure to the configuration of the main memory cells MC are arrayed at intersections of rows and columns, so as to obtain a reference cell array. The access transistors of respective reference cells RC are respectively connected to reference word lines RSWL0 and RSWL1. One terminal of a ferroelectric capacitor of each reference cell RC is connected to the reference plate line RPL. The other terminal of the ferroelectric capacitor of each reference cell RC is connected to a bit line (e.g., BL0, BL1, BL2, BL3) through its respective access transistor M1.
The reference word line decoder and driver circuits 12a and 12b are connected with the reference word lines RSWL0 and RSWL1, to provide a reference word line enable signal to the respective access transistors M1 of the reference cells RC via reference word lines RSWL0 and RSWL1.
The reference plate line driver circuit 14 provides a reference plate line enable signal having a predetermined level to the reference plate lines RPL in response to a reference plate line driver enable signal.
The sense amplifiers S/A are connected to corresponding pairs of bit lines (BL0, BL1, BL2 and BL3) that are commonly connected with the main memory cells MC and the reference cells RC, and compare a voltage level of main bit line BL connected to the main memory cell MC with a voltage level of a “sub-bit line” BLB (which may alternately be a predetermined one of bit lines BL0, BL1, BL2 and BL3) connected to the reference cell, and senses it, and then reads out data of a selected main memory cell.
Herewith, for an explanatory convenience, the bit line BL0 connected to the memory cell 20 is called a main bit line “BL”, while bit line BL1 connected to a reference cell 10a is called a sub-bit line BLB. The main bit line BL refers to a bit line (e.g., BL0, BL1, BL2 or BL3) connected to a memory cell MC selected to be read, and the sub-bit line BLB indicates a bit line (e.g., BL0, BL1, BL2 or BL3) connected to a reference cell RC for providing a reference voltage corresponding to the selected (selected to be read) memory cell MC.
Additionally, transistors N1, N2, N3 and N4 may be configured to precharge the bit lines BL0, BL1, BL2 and BL3.
FIG. 4 is a timing diagram illustrating the timing of a read data operation of a main memory cell in the conventional ferroelectric memory device of FIG. 3.
A read operation for data stored in memory cell 20 of FIG. 3 connected to a bit line BL0 will be described section by section, as follows. Herein, for convenience, the bit line BL0 connected to the memory cell 20 is called a main bit line BL, and the bit line BL1 connected to reference cell 10a is called a sub-bit line BLB. The main bit line BL indicates the bit line connected to a memory cell MC selected for a current read operation, and the sub-bit line BLB indicates the bit line connected to a reference cell RC to provide a reference voltage corresponding to the selected memory cell MC. The different voltage level signals detectable on the main bit line and sub-bit line for two alternate cases (e.g., data ‘1’ stored, and data ‘0’ stored in memory cell 20) are depicted at the bottom of FIG. 4.
As shown in FIGS. 3 and 4, before a read operation starts, precharge signals BL_PR and RBL_PR of a main bit line BL (connected to a memory cell 20) and of a sub-bit line BLB (connected to a reference cell 10a) are enabled (active high) to precharge bit lines BL and BLB.
At section “I”, when a chip selector signal CS is enabled (active high) and a read operation starts, main bit line BL and sub-bit line precharge signals BL_PR and RBL_PR are disabled. Simultaneously, the bit lines BL and BLB and the sense amplifier(s) S/A are electrically connected through switches (e.g., field effect transistors, FETS) by switch-control signals SA_PATH and RSA_PATH.
Next, a selected word line SWL0 and a corresponding reference word line RSWL1 are enabled (by a word line enable signal and a reference word line enable signal).
At section “II”, when a plate line PL and a reference plate line RPL are enabled (to a voltage having a predetermined level), a voltage corresponding to data ‘1’ or data ‘0’ of a selected main memory cell 20 is excited (passed) to the main bit line BL, and a reference voltage is provided to the sub-bit line BLB connected to reference cell 10a. 
At section “III”, a sense amplifier S/A is driven by a sense amplifier enable signal SAEN, and data of the memory cell 20 is sensed and amplified based on the reference voltage.
At section “IV”, before the data sensing operation of the sense amplifier S/A is completed, a sub-bit line precharge signal RBL_PR is enabled so as not to invert data of the reference cell 10a when data stored in the memory cell 20 is ‘0’.
At section “V”, reference plate line RPL and the plate line PL0 are disabled, then word line SWL0 is disabled, and the data of the memory cell 20 returns to original data (e.g., the data value just sensed is written back into the memory cell MC). Then, a main bit line precharge signal BL_PR is enabled, and a sense amplifier enable signal SAEN is disabled. Next, a chip selector signal CS is disabled. A read operation of data stored in the memory cell 20 is thus performed.
FIG. 5 is a block diagram of ferroelectric memory device having a reference voltage supply apparatus that employs conventional non-switching capacitance and switching capacitance.
As shown in FIG. 5, a ferroelectric memory device having a conventional reference voltage generating apparatus 30 includes a main memory cell array having a plurality of ferroelectric memory cells MC, word line decoder and driver circuits 42a, 42b, 42c and 42d, a plate line driver circuit 44, a reference voltage supply apparatus 30 that has a reference cell array 30a having a plurality of reference cells (e.g., 31a and 33a), and sense amplifiers S/A. To simplify the illustration, the reference cells connected to the bit lines BL1 and BL3 are not shown in FIG. 5.
The main memory cell array is constructed of memory cells having the same structure as the memory cell of FIG. 2. Thus, respective memory cells MC are constructed of one ferroelectric capacitor CFE and one access switch (access transistor M1) and are arrayed on intersections of word lines SWL0, SWL1, SWL2 and SWL3 and bit lines BL0, BL1, BL2 and BL3. An access transistor (switch) in each memory cell MC is connected to one word line (e.g., SWL0, SWL1, SWL2, or SWL3). One terminal of the ferroelectric capacitor in each memory cell MC is connected to the plate line PL0, and the other end (terminal) thereof is connected to a bit line (e.g., BL0, BL1, BL2, or BL3) through the access transistor M1.
The word lines SWL0, SWL1, SWL2, and SWL3 are respectively connected to each of word line decoder and driver circuits 42a, 42b, 42c, and 42d. The plate line PL0 is connected to a plate line driver circuit 44 that provides a plate line enable signal to the plate line PL0 in response to a plate driver enable signal.
The reference voltage supply apparatus 30 includes a reference cell array, reference word line decoder and driver circuits (e.g., 32) for providing a reference word line enable signals to reference word lines (e.g., RSWL0), and a reference plate line driver 34 for providing a reference plate line enable signal to the reference plate line RPL. The reference voltage supply apparatus 30 also includes circuits for generating various controls signals RP, RS and EQ.
Reference cells 31a and 33a having the same as or similar structure to that of the main memory cell MC are arrayed at intersections of the rows and columns, to obtain the reference cell array.
The reference cell array 30a includes a first reference cell 33a and a second reference cell 31a. The first reference cell 33a is constructed of one ferroelectric capacitor CREF0, one access switch (access transistor N33) and one control switch (control transistor N34), and stores/provides a voltage corresponding to a non-switching capacitance to bit line BL2 (when BL2 is employed as a sub-bit line). The second reference cell 31a is constructed of one ferroelectric capacitor CREF1, one access switch (access transistor N31) and one control switch (control transistor N32), and provides a voltage corresponding to a switching capacitance to bit line BL0 (when BL0 is employed as a sub-bit line).
The ferroelectric capacitors CREF1, and CREF0 and the access transistors N31 and N33 constituting the first reference cell 33a and the second reference cell 31a have the same as or similar to the configuration of a ferroelectric main memory cell MC, and are connected to the same reference word line (RSWL0) and to a reference plate line RPL. Each access switch (transistor N31 and N33) is connected to a reference word line RSWL0. One end (terminal) of the ferroelectric capacitor of each reference cell RC is connected to a reference plate line RPL, and the other end(terminal) thereof is connected to a bit line (BL0 or BL2) through an access switch (e.g., access transistor N31 or N33).
The control switches (transistors N32 and N34) are controlled by control signal RP. The control switch (transistor N34) of the first reference cell 33a is connected between one terminal of the ferroelectric capacitor CREF0 and a ground voltage. The control switch (transistor N32) of the second reference cell 31a is connected between one terminal of the ferroelectric capacitor CREF1, and a line to which the control signal RS is applied.
The reference word line decoder and driver circuit 32 is connected to and drives a reference word line RSWL0, and provides a reference word line enable signal to the reference word line RSWL0.
The reference plate line driver circuit 34 provides reference plate line enable signals having a predetermined level to the reference plate lines RPL in response to a reference plate line driver enable signal.
The control signal EQ controls a equalization control switch (transistor N9), to obtain a mean (combined, averaged) value of the reference voltage(s) provided on the bit lines BL0 and BL2 in the reference cell array 30a and provides that averaged voltage to the sense amplifier(s) S/A. The sense amplifier can reliably discriminate between a “0” and “1” voltage signal on the BL if a reference voltage, midway (averaged) between a “0” and a “1” signal, is provided for the sense amplifier.
The sense amplifiers S/A are connected corresponding to bit lines BL0, BL1, BL2 and BL3 that are commonly coupled with the main memory cells MC and with the reference cells (e.g., 31a and 33a), and compare a voltage level of the main bit line BL (connected to the main memory cell MC) with a voltage level of the sub-bit line BLB (connected to the reference cell), and sense it, and then read out the data of a selected main memory cell MC.
Additionally, transistors N5, N6, N7 and N8 may be configured to precharge the bit lines BL0, BL1, BL2 and BL3.
The reference cell connected to the BL0 has a ferroelectric capacitor storing a first logic state (e.g., “1”), and the reference cell connected to the BL2 has a ferroelectric capacitor storing a second logic state (e.g., “0”). Both capacitances of the ferroelectric capacitors of the reference cells may be identical in size to the capacitance of the memory cell capacitor. Each reference cell has an additional access switch (transistor) controlled by the control signal RP that is used to restore the original data state back into the reference cell after a read operation is complete.
FIG. 6 is a timing diagram illustrating the timing of a read operation for data stored in a main memory cell MC in the conventional ferroelectric memory device of FIG. 5.
By raising the RWL and the RPL, the first reference cell 31a generates voltage V1 on sub-bit line BL0 while the second reference cell 33a generates voltage V2 on sub-bit line BL2. Meanwhile, the accessed (selected) memory cells MC (e.g., 40) generate their own data on BL1 and BL3. Next, BL0 and BL2 are shorted together by raising EQ momentarily to share their charge. This results in a common reference voltage on both BL and BL that is equal to (V1+V2)/2, which is their average (mean) voltage. Then, the sense amplifiers are activated (by SAEN). At the end of a read operation, the first logic state (e.g., “1”) is restored (rewritten) in the reference cell 31a and the second logic state (e.g., “0”) is restored (rewritten) in the reference cell 33a, for the next read. This restoration of the original data of the reference cells is achieved by pulsing the RP and the RS as shown in FIG. 6.
A read operation for data stored in a memory cell 40 connected to bit line BL1 of FIG. 5 will be described section by section, as follows. For explanatory convenience, bit line BL1 connected to the memory cell 40 is called a main bit line BL, and bit lines BL0 and BL2 connected to a selected reference cell (e.g., 31a or 33a) (and to each other through control transistor N9) are called a sub-bit lines BLB. The main bit line BL indicates a bit line connected to a memory cell MC selected for a read operation, and the sub-bit line BLB indicates a bit line (or bit lines) connected to reference cells to provide a reference voltage corresponding to the selected memory cell MC.
As shown in FIGS. 6 and 5, before a read operation starts, precharge signal BL_PR (of a main bit line BL connected to a memory cell 40 and of a sub-bit line BLB connected to a reference cell 31a) is enabled to precharge bit lines BL and BLB (e.g., to the ground voltage).
At section “I”, when a chip selector signal CS is enabled and a read operation starts, bit line precharge signal BL_PR is disabled. Simultaneously, the bit lines BL0, BL1 and BL2 are electrically connected to the sense amplifier S/A by switches operated (closed) by control signal SA_PATH.
Next, a word line SWL1 and a reference word line RSWL0 (selected by a word line enable signal and a reference word line enable signal, respectively) are enabled.
At section “II”, when a plate line PL and a reference plate line RPL are enabled to a voltage having a predetermined level, a voltage Vx corresponding to data ‘1’ or data ‘0’ stored in the selected main memory cell 40 is excited (passed) to the main bit line BL, and an (averaged) reference voltage is provided to the sub-bit line BLB connected to the reference cell 31a. A reference voltage corresponding to a non-switching capacitance provided from the first reference cell 33a is provided to sub-bit line BL2, and a reference voltage corresponding to a switching capacitance provided from the second reference cell 31a is provided to sub-bit line BL0. When the two reference voltages are provided to a sub-bit lines BLB (e.g., bit lines BL2 and BL0), a control signal EQ is enabled, to operate (close) the control transistor N9 and so provide a mean (averaged) value of the two reference voltages provided on the bit lines BL0 and BL2, (to the sub-bit lines BLB, e.g., BL0 and BL2). Then, the control signal EQ is disabled.
At sections “III” and “IV”, the sense amplifier S/A is driven by a sense amplifier enable signal SAEN, and the stored data of the memory cell 40 is sensed and amplified based on the reference voltage.
At section “V”, the reference plate line RPL and the plate line PL0 are disabled, then word line SWL1 is disabled, and the data of the memory cell 40 contains stored data it contained prior to the read operation. Also, the reference word line RSWL0 is disabled and a control signal RP is enabled, to drive the control transistors N32 and N34. Thus, in the first reference cell 33a, data corresponding to non-switching capacitance is maintained, and in the second reference cell 31a, data corresponding to switching capacitance is maintained by an enabled control signal RS. Next, bit line precharge signal BL_PR is enabled, and the sense amplifier enable signal SAEN is disabled. Then, chip selector signal CS is disabled. Thereby a read operation of data stored in the memory cell 40 is performed.
In such a reference voltage supply apparatus described above it is important to provide a stabilized reference voltage. However, in the conventional reference voltage supply apparatus referred to in FIGS. 3 to 6, ferroelectric non-switching capacitance is used. In this case a polarization state is maintained in the reference cells for a long time, which causes an imprint effect in the reference cells.
The imprint effect denotes that in case a ferroelectric is maintained in one polarization state for a long time, a hysteresis curve shifts to one side along the voltage axis. The ferroelectric memory cell having the imprint effect has state points located differently from the initial state points before the imprint effect occurrence, by the shift, thus causing a reference voltage change of a reference cell. This reduces the reliability of the ferroelectric device in a read operation.